1. Field of the Invention
This invention relates to switching power supplies, and more particularly to soft start during switch on of a plurality of power supplies connected in a system.
2. Background Information
Switching power supplies are often designed to produce one DC output voltage from a DC input source of power. When it is desired to have power supplied at a plurality of different DC voltages, a plurality of single voltage switching power supplies are assembled into a system, with each desired voltage supplied by a different switching power supply. The plurality of single voltage switching power supplies are then connected to the source of input DC power, and each supplies power at its designated output voltage.
A system designer assembles as many single voltage switching power supplies as he needs to supply power to the loads in the system. Often the loads are computer chips, that is the loads are a group of integrated circuits. The integrated circuits are often connected to the same system ground, and the integrated circuits are also connected together by signal leads between the integrated circuits. Thus, when voltage is applied by one of the switching power supplies to a particular integrated circuit, this voltage may appear across other of the integrated circuits.
xe2x80x9cSoft startxe2x80x9d of power supplies is a term used to describe bringing the output voltage of the power supply up gradually, usually bringing the voltage up as a linear function of time. When several switching poser supplies are connected in a system, it may be desired to bring up the various voltages in an orderly sequence, so that one voltage begins coming up before a different voltage becomes coming up. To bring up the various voltages up at different times requires that the different individual switching power supplies bring up their voltages at different times.
Since the integrated circuits being supplied by the different switching power supplies are all connected together, voltages different from normal operating voltages may develop between the integrated circuits during a soft start operation. Uncontrolled voltage differences caused by soft start of different switching power supplies may injure the integrated circuits. System designers use a variety of strategies to protect their integrated circuits during a soft start operation.
Turning now to FIG. 1, a typical arrangement 100 of a single switching power DC to DC converter power supply is shown. Power source 102 supplies DC power to the switching power supply 104 through connection 103. Typically, a switching power supply uses Field Effect Transistors (FETs) as switches, and the FETs are switched synchronously by the switching power supply 104. Such a switching power supply is often referred to as a Synch FET power supply. Synch FET power supply 104 supplies power to a load 106 through connection 105. The load is often an integrated circuit.
The Synch FET power supply receives power at an input voltage and input current through connection 103, and supplies power through connection 105 at an output voltage and output current, where the output voltage is typically different from the input voltage.
Turning now to FIG. 2A system 200 is a design using three single voltage synch FET power supplies 202, 203, 204 to supply power at three different voltages. For example, synch FET power supply 202 supplies power at 1.5 Volts to bus 202B, synch FET power supply 203 supplies power at 2.5 Volts to bus 203B, synch FET power supply 204 supplies power at 3.3 Volts to bus 204B. Typically, each synch FET power supply may supply from around 100 Watts to around 500 Watts of power. Input power supply line 206 supplies DC power to each of the synch FET power supplies 202, 203, 204 at a convenient input voltage.
Diode 210 and diode 212 are specified by a system designer in order to protect integrated circuits supplied by power by bus 202B, 203B, 204B during soft start of the power supplies.
Turning now to FIG. 2B, graphs 220 show voltage on bus 202B, 203B, 204B during soft start of the synch FET power supplies 202, 203, 204. First, the low voltage power supply is enabled at time 231, graph 222 rises linearly with time during portion 222A, and then stabilizes at the desired output voltage 1.5 Volt. Diode 210 pulls up bus 203B, and diode 212 pulls up bus 204B so that bus 203B and bus 204B follow bus 202B as synch FET power supply 202 is turned on using soft start. Both diodes 210 and 212 have an internal voltage drop, and so bus 203B voltage remains less than bus 202B voltage, and bus 204B voltage remains less than bus 203B voltage, as shown in graph 200, between time 231 and time 232.
At time 232 synch FET power supply 203 is turned on using soft start, and the voltage on bus 203B begins to rise as shown by graph 224. During segment 224A of graph 224 the voltage rises linearly and then stabilizes at the desired output voltage of 2.5 Volt.
Diode 210 prevents a current flow into bus 202B from 203B, and so bus 202B is not affected by activation of synch FET power supply 203, as shown by graph 222. However, diode 212 pulls up bus 204B so that the voltage on bus 204B follows that of bus 203B, but remains less by the voltage drop across diode 212, as shown by graph 226.
At time 223 synch FET power supply 204 is turned on by soft start. The voltage on bus 204B begins to rise linearly as shown by graph 226 at section 226A, and then stabilizes at the desired output voltage of 3.3 Volt. Diode 212 prevents current flow from bus 204B to bus 203B, and so the voltage of bus 203B is not affected by the rise of voltage applied by synch FET power supply 204 to bus 204B.
The use of diodes 210 and 212 by a system designer who combines a plurality of single voltage synch FET power supplies to supply a plurality of voltages to an integrated circuits as loads work by pulling up the un-activated power buses, and so the diodes prevent unwanted large voltage differences to develop across the loads, typically integrated circuit loads (not shown in FIG. 2A).
However, the diodes 210, 212 cause a problem in the un-activated synch FET power supplies, and the problem is called the xe2x80x9cback biasxe2x80x9d problem.
The back bias problem is illustrated in FIGS. 3A, 3B, 3C. FIG. 3A illustrates a synch FET DC to DC converter power supply 300. Input power and current are supplied on bus 302 at an input voltage Vin. Output power and current are supplied by the DC/DC converter 304 on output bus 305 at a desired output voltage Vout. A sense voltage line 308, shown as directly connected to output bus 305 is used by DC/DC converter 304 to monitor and control the output voltage on output bus 305. A reference voltage is supplied on line 306 to DC/DC converter 304. The DC/DC converter 304 regulates the output voltage to match the reference voltage on line 306.
FIG. 3B is a graph showing operation of synch FET DC to DC converter power supply 300 when the output voltage is pulled up above the reference voltage, as occurs through diodes 210 and 212 before the higher voltage synch FET power supplies are turned on.
Back bias voltage 310 is applied to the synch FET power supply, for example by a diode such as diode 210, 212. At time 312 the synch FET power supply 304 is turned off and the back bias voltage 310 has no effect. At time 314 synch FET power supply 304 is turned on and the reference voltage, shown as the dotted line graph 316, is less than the output voltage. The output voltage of synch FET 304 is driven down during segment 310A of graph 310 until time 318, and at time 318 the reference voltage is caused by control circuits (not shown) to rise linearly in order to implement soft start. Segment 310B of graph 310 shows the output voltage rising with the rise in reference voltage, as the reference voltage rises linearly with time. At time 320 the rise in reference voltage reaches its stable value, and the output voltage stabilizes at the desired output voltage Vout as shown by segment 310C of graph 310.
The drop in output voltage after time 314 shown by segments 310A and 310B of graph 310 is very undesirable. This drop in output voltage causes power to flow from the source of back bias voltage shown at time 312 into synch FET DC/DC converter 304.
Undesirable current flow, and also power flow, into synch FET DC/DC converter 304 is shown in FIG. 3C. Graph 350 shows current flow in and out of synch FET power supply 304. Segment 350A illustrates undesirable power flow into DC/DC converter 304 from output bus 305, where the source of power is the source of the back bias voltage shown by graph 310 at time 312. After time 354 the output voltage rises above the back bias, and power flow begins from, rather than to, DC/DC converter 304, as shown by segment 350B of graph 350.
It is desirable to design a synch FET power supply such as synch FET DC/DC converter 304 that can be connected in a system 200, and not have power flow into the synch FET DC/DC converter when a back bias is applied to the output bus 305 of the synch FET DC/DC converter.
Turning now to FIG. 4A, there is shown another system 400 arrangement which attempts to solve the voltage spread applied to integrated circuit loads during soft start, and also produces the back bias problem illustrated in FIGS. 3A, 3B, 3C. Representative integrated circuit loads are shown in the dotted line box 402 as IC1402A, IC2402B, and IC3402C.
Synch FET power supply 410 supplies bus 410B with a high voltage, for example 3.3 Volt. Synch FET power supply 412 supplies bus 412B with a medium voltage, for example 2.5 Volt. Synch FET power supply 414 supplies bus 414B with a low voltage, for example 1.5 Volt. Bus 410B supplies the high voltage to IC1402A. Bus 412B supplies the medium voltage to IC2402B. Bus 414B supplies the low voltage to IC3402C.
A system design 400 using the three synch FET power supplies 410, 412, 414 along with integrated circuits IC1402A, IC2402B, IC3402C is created by a systems designer. Bus 414B supplies the low voltage to IC3402C. In the absence of system design to protect the integrated circuits 402A, 402B, 402C, after bus 410B rises to its high voltage, for example 3.3 Volt, then signal lines 403 can apply the high voltage to IC3402C. IC3 is designed for a low voltage power supply provided by bus 414B, and so the high voltage supplied by bus 410B through signal lines 403 could damage or destroy IC3402C.
Likewise, as bus 410B rises to its high voltage operating voltage, signal lines 405 can apply the high voltage to IC2402B. Again, IC2402B may be damaged by the voltage applied by bus 410B, as IC2 is designed for a lower voltage ordinarily supplied by medium voltage bus 412B.
FIG. 4B is a graph showing soft start of the various synch FET power supplies 410, 412, 414. First, at time 420 the high voltage synch FET power supply 410 is enabled, and the voltage on bus 410B begins to rise, as shown by graph 410C. Linear regulator 422 brings up bus 412B, and linear regulator 424 brings up bus 414B. The linear regulators 422, 424 protect the load integrated circuits 402A, 402B, 402C by insuring that no large voltage difference exceeding the design limits of the integrated circuits is applied by the overall system 400 to an integrated circuit.
Then at time synch FET power supply 412 is turned on using soft start. And at time 424 synch FET power supply 414 is turned on using soft start.
Again, however, a back bias is applied to each of the lower voltage synch FET power supplies as the higher voltage synch FET power supply is enabled during soft start. As illustrated in FIGS. 3A, 3B, 3C power will flow into the back biased synch FET power supply as that synch FET power supply is enabled using soft start.
There is needed a design of a synch FET power supply that can be connected in a system, and not have power flow into the synch FET power supply when a back bias is applied to the output bus of the synch FET power supply during soft start, where the back bias exceeds the desired output voltage for a period of time.
A synch FET power supply uses a plurality of electronic switches to periodically connect the primary of a transformer to a DC input source of power, and to periodically reverse the primary connection to the source of DC power so as to cause the primary of the transformer to generate a time varying magnetic field. The time varying magnetic field is coupled to two secondary windings. In an exemplary embodiment of the invention, the secondary can be center tapped, and the center tap provides one of the output terminals of the synch FET power supply. An electronic switch connected to each secondary winding periodically connects its secondary to the other output terminal. The switches are timed so that, for example, the center tap output terminal is the positive DC output terminal, and the other ends of the two secondary windings provide the negative DC output terminal. A reference voltage is applied to the control circuits, and the control circuits adjust the switches so that the output voltage tracks the reference voltage.
Logic AND gates control the xe2x80x9cturn onxe2x80x9d signals to the electronic switches in the secondary circuits so that the secondary windings are not connected to an output terminal until a xe2x80x9csynch FET enablexe2x80x9d signal is applied to the AND gates. During soft start, the secondary windings remain disconnected from an output terminal until a xe2x80x9csynch FET enablexe2x80x9d signal is applied to an input of the logic AND gates, and since the secondary windings do not provide a complete circuit between the output terminals, no power flows into the synch FET power supply even though a back bias is applied between the output terminals by another power source.
In another aspect of the invention, a filter is placed between the output of the AND gates and the switches which they drive. The filter turns off the switches when the AND gate remains on for a long time, and the filter prevents very short pulses from being applied to the switches.